Functional simulation for FPGA designs needs all design components to be defined in the main working library. For designs that are based on FPGA resources or primitives, these primitives shall be defined in the simulation working library also.
In this guide, we will see how to use Xilinx primitives in a functional simulation using QuestaSim/ModelSim. Scrol down below or simply download it as PDF.
1 - Using ISE Flow 2- Using Vivado Design Flow