Quite old information or background, but people who started to work using Xilinx ISE flow had more luck to understand Vivado flow seamlessly when they migrated from ISE to Vivado. Nevertheless, Other FPGA tools from other Venodrs has similar synthesis and implementation flow and stages. Therefore, an overview of different tools used in Xilinx ISE flow maybe useful for some people who might still working with ISE or would like to have comparison between old Xilinx methodology and recent tools.